1. Field of the Invention
The present invention relates to a refreshing system for dynamic memory, and more particularly to a system that the refresh request frequency is made variable according to the ambient temperature thereby improving the throughput of the system having such memory.
2. Description of the Prior Art
In the conventional refreshing system of a dynamic memory, the central processing unit, upon granting the request for refreshing from the memory, transfers the bus line control to the memory during the refreshing cycle. Now reference is made to FIG. 1 for explaining such a conventional refreshing system in which there is shown a refresh clock generator RCG composed, for example, of an astable multivibrator, a dynamic random access memory DRM, a dynamic RAM controller DRC composed, for example of Motorola MC3480, for controlling said memory DRM, a counter RCT for generating the address of the random access memory DRM to be refreshed, an address multiplexer MPX for switching the address information released from the central processing unit CPU through an address bus B1, a counter output signal released from the refresh counter through a refresh bus B2 in response to a refresh signal REF from the controller DRC, a data bus B3 between the memory DRM and the central processing unit CPU, a row address strobe signal line RAS, a column address strobe signal line CAS, and signal lines S1-S5.
The refresh clock generator RCG supplies, through the signal line S1 to the controller DRC and the refresh counter RCT, refresh clock pulses RC of a determined frequency as shown in FIG. 2. In response to the leading edge of each refresh clock pulse RC, the controller RC generates a refresh request signal RREQ as shown in FIG. 2 which is supplied to the central processing unit CPU through the signal line S2. In response to said refresh request signal RREQ, the central processing unit CPU grants the transfer of bus line control to the memory and releases a refresh grant signal RGRT shown in FIG. 2 to the controller DRC through the signal line S3. In response to the trailing edge of said grant signal RGRT, the controller DRC releases a refresh signal REF shown in FIG. 2 through the signal line S4 to the address multiplexer MPX which is thus switched from the CPU address bus line B1 to the RCT bus line B2. The memory DRM is refreshed while it is switched to the bus line B2. Also the refresh counter RCT is step advanced at the trailing edge of the refresh clock pulse RC to retain the succeeding refresh address. The signal line S5 is utilized for sending the read/write signal R/W from the central processing unit CPU to the memory DRM.
Such a conventional refreshing method as explained above is defective in that the refreshing interval of the dynamic RAM varies depending on the ambient temperature. As an example, the curve A in FIG. 3 shows the relation between the refreshing interval (R.I.) and the ambient temperature (Ta) in case of a 4K-bit dynamic RAM 2107A supplied by Intel Corp. As will be seen from this curve, the refreshing interval, which is as short as 10 ms at 70.degree. C., becomes as sixty times long as 600 ms at 0.degree. C.